To meet the requirements for faster performance, the characteristic dimensions of features of integrated circuit devices have continued to be decreased. Manufacturing of devices with smaller feature sizes introduces new challenges in many of the processes conventionally used in semiconductor fabrication.
As a result of the size decrease in these products, the components that comprise the products must also become smaller and/or thinner. Examples of some of those components that need to be reduced in size or scaled down are microelectronic chip interconnections, semiconductor chip components, resistors, capacitors, printed circuit or wiring boards, wiring, keyboards, touch pads, and chip packaging.
When electronic and semiconductor components are reduced in size or scaled down, any defects that are present in the larger components are going to be exaggerated in the scaled down components. Thus, the defects that are present or could be present in the larger component should be identified and corrected, before the component is scaled down for the smaller electronic products. As feature sizes in integrated circuits are reduced to below about 0.15 μm in future generations of devices, problems such as RC delays and signal-crosstalk will become a dominant problem.
In order to identify and correct defects in electronic, semiconductor and communications components, the components, the materials used and the manufacturing processes for making those components should be broken down and analyzed. Electronic, semiconductor and communication/data-exchange components are composed, in some cases, of layers and films of materials, such as metals, metal alloys, dielectric layers, ceramics, inorganic materials, polymers, or organometallic materials.
One of the viable solutions to overcome the problems with integrated circuits mentioned before is to use low dielectric constant (k) materials with dielectric constants of less than about 3 for interlevel (ILD) and intermetal (IMD) dielectric applications. One of the major roadblocks is the mechanical strength of a—low dielectric constant (k) silicon-containing materials. Typically, mechanical strength is proportional to the density of such material. However, the density does not change for a given chemical composition at a given dielectric constant. In this case, the strength of the nanoporous silica is maximized by having the highest degree of cross-linking.
Single level metal patterned wafers with inorganic dielectrics showed voids between the copper lines. These voids form because of the material needing to rearrange itself due to chemical changes that make it less capable of handling the stress placed upon it by the surrounding metals. The voids are by nature unpredictable in size and shape and are dictated by the amount of stress placed upon the dielectric space as well as the inherent flaws within that space. These voids are undesirable because they are unpredicatable and will degrade yield and reliability of the circuit.
U.S. Pat. No. 6,208,014, which is commonly owned and assigned to Honeywell International Inc and also which is incorporated herein in its entirety, teaches a film formation process wherein a silica dielectric film is reacted with a multifinctional surface modification agent. This patent teaches that the nanoporous silica film may be prepared on a substrate immediately prior to the treatment or may be previously prepared and stored or obtained from another source. The patent also teaches that the film may be aged, e.g., further cross-linking/condensation, prior to modification. However, the patent does not teach the voiding problem or that such surface modification treatment may be used on an integrated film.
Therefore, it would be ideal to a) identify potential causes of voiding; b) developing methods and compositions to repair identified voiding or “pre-voiding”; and c) utilize conventional compositions and methods that do not increase the cost or complexity of the semiconductor production process that taken alone or in combination would be desirable to advance the production of layered materials, electronic components and semiconductor components. There is also a need to develop either new materials with enhanced and improved properties, such as 1) lower porosity at similar dielectric constants and 2) contains organic moieties that are more resilient to the integration process conditions; or a process that could help to “repair” the damage done to the films by reintroducing carbon-moieties and to “restore” the properties of low—k dielectric films.